This invention relates to the implementation of support for a new Real Space Control bit with an existing Translation Lookaside Buffer in a microprocessor system.
As is generally known, computers use a variety of addressing schemes to access storage memory to retrieve instructions and data. The address actually applied to the storage memory is often referred to as an absolute address, an effective address is the address actually referred to by programmers, and a virtual or real address is a type of effective address.
Because programmers generally refer to an effective address when constructing computer programs, the effective address must be determined to be a virtual address or a real address and then translated to an absolute address before main storage memory can be accessed. To achieve increased computer performance and speed, this address translation process must be efficiently performed.
Each address translation involves a multi-stage process and consumes valuable processor cycles. A conventional solution to speed up this address translation is to utilize an address translation cache called a translation lookaside buffer (TLB) which stores the most recent translations. Using an address translation cache skips some of the steps of address translation from the virtual address to the absolute address. In this way, the processor need only access the TLB to obtain the address of the most recently utilized translations.
A translation lookaside buffer (TLB) contains two main types of translation entries: translations that convert a real storage address to an absolute storage address (real mode translation), and translations that convert a virtual storage address with a region or segment table origin to an absolute address (known as dynamic address translation or DAT). Real mode translation is a simple mode of translation requiring only a real address to start translation. On the other hand, DAT is a more complex translation mode requiring a virtual address and a starting Region or Segment Table Origin (RTO or STO) in order to do one or more storage table lookups.
To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer (TLB), an existing control bit, the Private Space (PS) bit, in the TLB is replaced by a new control bit, the Ignore Common segment (IC) bit, to create new non-overlapping TLB entries. Support for the RSC bit, which changes address translation modes, is achieved by combining it with the PS bit and establishing the new IC control bit as an interlock. Based upon the status of these and other control bits, address translations are interlocked or enabled.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.